Stress-inducing silicon liner in semiconductor devices

A method, comprising:

• providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;
• forming a silicon layer over the semiconductor device;
• forming an interlayer dielectric (ILD) layer over the silicon layer, wherein the ILD layer includes excess oxygen;
• annealing the ILD layer, thereby converting the silicon layer to a compound of silicon and oxidized silicon;
• after annealing the ILD layer, introducing a dopant species to the ILD layer;
• and
• after introducing the dopant species, performing a thermal treatment to the doped ILD layer, thereby converting the compound of silicon and oxidized silicon to a fully oxidized silicon layer.

A method, comprising:

• providing a semiconductor device that includes a dummy gate structure disposed over a substrate and source/drain (S/D) features disposed adjacent to the dummy gate structure, wherein the dummy gate structure traverses a channel region between the S/D features;
• forming an etch-stop layer (ESL) over the semiconductor device, wherein the ESL is directly above the S/D features;
• forming a silicon liner over a top surface of the ESL, wherein the silicon liner includes elemental silicon;
• forming an interlayer dielectric (ILD) layer over the silicon liner;
• introducing a dopant species to the ILD layer;
• and
• performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner.