Thin film transistor including a compositionally-graded gate dielectric and methods for forming the same

A semiconductor device comprising a thin film transistor located over a substrate, wherein the thin film transistor comprises:

• a gate electrode overlying a substrate;
• a stack of a gate dielectric and an active layer comprising a semiconducting metal oxide material, the stack overlying the gate electrode, wherein the active layer has a substantially uniform thickness throughout between a first horizontal plane including a bottom surface of the active layer and a second horizontal plane including a top surface of the active layer;
• and
• a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer;
• a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer;
• and
• a top gate electrode overlying the top gate dielectric, wherein an entire area of each sidewall of the gate dielectric is directly contacted by the top gate dielectric.

A semiconductor device comprising a thin film transistor located over a substrate, wherein the thin film transistor comprises:

• an insulating layer embedding a gate electrode and overlying a substrate;
• a stack of a gate dielectric and an active layer comprising a semiconducting metal oxide material, the stack overlying the gate electrode;
• a dielectric layer overlying the insulating layer and laterally surrounding the stack;
• a top gate dielectric contacting a portion of a top surface of the active layer, portions of the pair of lengthwise sidewalls of the active layer, a segment of a top surface of the gate electrode that does not have an areal overlap with the active layer, and a segment of a top surface of the insulating layer, wherein a pair of sidewalls of the top gate dielectric extends along a direction that is perpendicular to a separation direction between the source electrode and the drain electrode from the segment of the top surface of the gate electrode to the segment of a top surface of the insulating layer;
• and
• a top gate electrode overlying the top gate dielectric, wherein each of sidewalls of the top gate electrode are vertically coincident with a respective sidewall of the top gate dielectric, and each of the sidewalls of the top gate electrode has a respective bottom edge that coincides with a respective edge of the top gate dielectric.