Semiconductor device

A semiconductor device, comprising:

• a first active region, a second active region and a third active region respectively arranged across a substrate in a first direction, the first active region and the second active region having different conductivity types, and the second active region and the third active regions having a same conductivity type;
• a device isolation layer on the substrate and defining a first active pattern on the first active region, a second active pattern on the second active region, and a third active pattern on the third active region;
• a gate electrode extending in the first direction to cross the first, second, and third active patterns;
• a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern respectively provided on the first active pattern, the second active pattern and the third active pattern, wherein each of the first source/drain pattern, the second source/drain pattern, and the third source/drain pattern is adjacent to a side of the gate electrode;
• an interlayer insulating layer on the gate electrode;
• a first active contact electrically connected to the first source/drain pattern and the second source/drain pattern;
• a second active contact electrically connected to the third source/drain pattern;
• and
• a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact,
• wherein upper surfaces of the buffer layer, the first and second active contacts, and the interlayer insulating layer all lie in a same plane, and
• wherein the buffer layer comprises a material having an etch selectivity with respect to the interlayer insulating layer.

A semiconductor device, comprising:

• a first logic cell on a substrate including a PMOSFET region and an NMOSFET region spaced apart in a first direction, a first border, a second border, a third border and a fourth border, the first border and the second border opposing each other in a second direction crossing the first direction, and the third border and the fourth border opposing each other in the first direction;
• a device isolation layer defining a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region, the first active pattern and the second active pattern extending in the second direction, a first upper portion of the first active pattern protruding above the device isolation layer, and a second upper portion of the second active pattern protruding above the device isolation layer;
• a gate electrode extending in the first direction to cross the first and second active patterns;
• a first source/drain pattern provided in the first upper portion of the first active pattern and a second source/drain pattern provided in the second upper portion of the second active pattern, wherein each of the first source/drain pattern and the second source/drain pattern is adjacent to a side of the gate electrode;
• a division structure provided on at least one of the first border and the second border;
• a gate spacer provided on the side of the gate electrode;
• a gate capping pattern provided on a top surface of the gate electrode;
• an interlayer insulating layer provided on the gate capping pattern;
• a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern, and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern;
• a buffer layer extending in the second direction between the PMOSFET region and the NMOSFET region, provided in an upper region of the interlayer insulating layer, and interposed between the first active contact and the second active contact;
• silicide patterns respectively interposed between the first active contact and the first source/drain pattern, and between the second active contact and the second source/drain pattern;
• a gate contact penetrating the interlayer insulating layer and the gate capping pattern and connect the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer including a first power line extending in the second direction and provided on the third border, a second power line extending in the second direction and provided on the fourth border, and first interconnection lines provided between the first power line and the second power line, wherein the first interconnection lines are electrically and respectively connected to the first active contact, the second active contact and the gate contact;
• and
• a second metal layer on the first metal layer, the second metal layer including second interconnection lines extending in the first direction and electrically connected to the first metal layer.