Semiconductor device with guard ring isolating power device

A semiconductor device, comprising:

• a power device, which is disposed on a substrate, and comprising a gate electrode, a source electrode, and a drain electrode;
• and
• a guard ring structure which is configured to surround the power device,
• wherein the guard ring structure comprises:
• an N-type first guard ring disposed adjacent to the power device;
• a P-type second guard ring disposed adjacent to the N-type first guard ring;
• and
• an N-type third guard ring disposed adjacent to the P-type second guard ring, and
• wherein the N-type first guard ring, the P-type second guard ring, and the N-type third guard ring are configured to receive a same first bias,
• wherein the power device comprises an N-type buried layer disposed in the substrate and an N-type deep well region configured to be in contact with lower portions of the first guard ring, the second guard ring, and the third guard ring, and
• wherein the N-type deep well region is disposed between the guard ring structure and the N-type buried layer.

A semiconductor device, comprising:

• a power device;
• a circuit block region;
• a guard ring structure, configured to surround the power device,
• a P-type well region, configured to surround the guard ring structure, and disposed between the circuit block region and the guard ring structure,
• a first buried layer of a first conductivity type disposed in a substrate;
• and
• a deep N-type well region disposed in the substrate between the guard ring structure and the first buried layer of a first conductivity type,
• wherein the guard ring structure comprises:
• an N-type first guard ring;
• a P-type second guard ring, and
• an N-type third guard ring.