Method and system of junction termination extension in high voltage semiconductor devices

A semiconductor device comprising:

• a semiconductor substrate comprising a first side and second side, wherein the semiconductor substrate is characterized by a first conductivity type;
• a first III-nitride epitaxial semiconductor layer epitaxially grown on the first side of the semiconductor substrate, wherein the first III-nitride epitaxial semiconductor layer is characterized by a varying dopant concentration of the first conductivity type;
• a second III-nitride epitaxial semiconductor layer epitaxially grown on the first III-nitride epitaxial semiconductor layer, wherein the second III-nitride epitaxial semiconductor layer is characterized by the first conductivity type and an upper surface, wherein the second III-nitride epitaxial semiconductor layer comprises a contact region including a contact structure comprising a plurality of source contacts, each of the plurality of source contacts formed on a portion of the upper surface of the second III-nitride epitaxial semiconductor layer;
• a plurality of fins formed in the second III-nitride epitaxial semiconductor layer and a portion of the first III-nitride epitaxial semiconductor layer, wherein bottom surfaces of the fins extend from the first III-nitride epitaxial semiconductor layer and each of the plurality of fins is separated from an adjacent fin of the plurality of fins by a trench;
• a third III-nitride epitaxial semiconductor layer epitaxially regrown in the trenches separating the plurality of fins and defined by an upper surface coplanar with the upper surface of the second III-nitride epitaxial semiconductor layer and including a terminal region surrounding the contact region, wherein the terminal region comprises a tapered junction termination element having a linear profile and a non-conducting ion implanted zone adjacent to the tapered junction termination element, wherein the non-conducting ion implanted zone is characterized by the linear profile, and wherein the third III-nitride epitaxial layer is characterized by a second conductivity type opposite to the first conductive type;
• and
• a gate metal layer formed on the upper surface of the third III-nitride epitaxial semiconductor layer.