Diode chip

A diode chip, comprising:

• a semiconductor chip;
• a region separation structure, dividing the semiconductor chip into a first device region and a second device region;
• a first pin junction portion, formed on a surface of the first device region with a first polarity direction, wherein the first pin junction portion comprises a first P layer, a first I layer over the first P layer and a first N layer over the first I layer, and the first N layer is exposed at a surface of the semiconductor chip;
• a first rectifier pair, comprising a first pn junction portion and a first reversed pin junction portion, wherein the first pn junction portion is separated from the first pin junction portion and formed in the first device region with the first polarity direction, and the first reversed pin junction portion is connected to the first pn junction portion in reversed direction and formed on the surface of the first device region with a second polarity direction, wherein the first reversed pin junction portion comprises a second N layer, a second I layer over the second N layer and a second P layer over the second I layer, and the first pn junction portion and the first reversed pin junction portion share the second N layer;
• a first junction separation trench, formed in the first device region and between the first pin junction portion and the first rectifier pair in a manner of separating the first pin junction portion and the first rectifier pair;
• a second pin junction portion, formed on a surface of the second device region with the first polarity direction, wherein the second pin junction portion comprises a third P layer, a third I layer over the third P layer and a third N layer over the third I layer, and the third N layer is exposed at the surface of the semiconductor chip;
• a second rectifier pair, comprising a second pn junction portion and a second reversed pin junction portion, wherein the second pn junction portion is separated from the second pin junction portion and formed in the second device region with the first polarity direction, and the second reversed pin junction portion is connected to the second pn junction portion in reversed direction and formed on the surface of the second device region with the second polarity direction, wherein the second reversed pin junction portion comprises a fourth N layer, a fourth I layer over the fourth N layer and a fourth Player over the fourth I layer, and the second pn junction portion and the second reversed pin junction portion share the fourth N layer;
• and
• a second junction separation trench, formed in the second device region and between the second pin junction portion and the second rectifier pair in a manner of separating the second pin junction portion and the second rectifier pair;
• wherein the first rectifier pair and the second rectifier pair are disposed between the first pin junction portion and the second pin junction portion and between the first junction separation trench and the second junction separation trench;
• and
• wherein the first pn junction portion comprises the second N layer and a fifth P layer under the second N layer, and the second N layer and the fifth P layer are separated from the first P layer by the first junction separation trench, and the second pn junction portion comprises the fourth N layer and a sixth Player under the fourth N layer, and the fourth N layer and the sixth Player are separated from the third P layer by the second junction separation trench.