Symmetric FET for RF nonlinearity improvement

A method for reducing OFF state parasitic capacitance of a field effect transistor (FET) operating as a radio frequency (RF) switch, the method comprising:

• arranging a gate structure in a medial region of a planar layout of the FET;
• arranging a source structure and a drain structure in respective opposite edges of the planar layout;
• projecting gate fingers outwardly from the gate structure towards the opposite edges;
• projecting interdigitated source and drain structures inwardly from respective source and drain structures towards respective opposite edges and along the gate fingers;
• crossing pairs of the interdigitated source and drain structures in the medial region where the gate structure is arranged;
• based on the crossing, reversing a sequence of the interdigitated source and drain structures along the gate fingers, thereby providing a symmetry in RF voltages coupled to structures of the FET in the OFF state;
• and
• based on the symmetry in the RF voltages, reducing parasitic capacitance
• wherein a total number of gate fingers that project outwardly towards one of the respective opposite edges is equal to a total number of gate fingers that project outwardly towards the other of the respective opposite edges.

A symmetric field effect transistor (FET) comprising:

• a gate structure arranged in a medial region of a planar layout of the symmetric FET;
• a source structure and a drain structure arranged in respective opposite edges of the planar layout;
• gate fingers that project outwardly from the gate structure towards the opposite edges;
• and
• interdigitated source and drain structures that project inwardly from respective source and drain structures towards respective opposite edges and along the gate fingers;
• and
• source and drain crossing structures arranged in the medial region where the gate structure is arranged, configured to provide crossings of pairs of the interdigitated source and drain structures so to reverse a sequence of the interdigitated source and drain structures along the gate fingers in a top half of the layout with respect to a bottom half of the layout
• wherein a total number of gate fingers that project outwardly towards one of the respective opposite edges is equal to a total number of gate fingers that project outwardly towards the other of the respective opposite edges.