Stress reduction apparatus and method

A structure comprising:

• a first integrated circuit die, the first integrated circuit die comprising:
• a substrate;
• an interconnect structure over the substrate;
• and
• a protection layer over the interconnect structure;
• a connector over the protection layer and electrically coupled to the interconnect structure;
• and
• a plurality of L-shaped dummy conductive regions over the protection layer, wherein corners of the plurality of L-shaped dummy conductive regions are aligned with respective corners of the first integrated circuit die in a plan view, and wherein the connector is located in a triangular region formed by a first L-shaped dummy conductive region of the plurality of L-shaped dummy conductive regions.

A structure comprising:

• a first integrated circuit die, the first integrated circuit die comprising:
• a substrate;
• and
• a polymer layer over the substrate;
• an under bump metallization structure over the polymer layer;
• a connector bonded to the under bump metallization structure;
• a first dummy plane over the polymer layer and adjacent to the under bump metallization structure, wherein an edge of the first dummy plane is collinear with a first edge of the polymer layer in a plan view;
• and
• a second dummy plane over the polymer layer and adjacent to the first dummy plane, wherein an edge of the second dummy plane is collinear with a second edge of the polymer layer in the plan view, wherein the first dummy plane and the second dummy plane form a triangular region, and wherein the connector is disposed in the triangular region, wherein the first dummy plane and the second dummy plane are conductive.