Memory devices and electronic systems

A memory device, comprising:

• a first structure comprising:
• an array region comprising:
• levels of volatile memory cells vertically stacked relative to one another, the volatile memory cells of each of the levels comprising:
• access devices;
• and
• storage node devices coupled to the access devices, each of the storage node devices vertically overlapping and horizontally neighboring a respective one of the access devices;
• and
• conductive pillars vertically extending completely through the levels of volatile memory cells, the conductive pillars coupled to the access devices of the volatile memory cells within the levels of volatile memory cells;
• and
• a conductive contact region horizontally neighboring the array region and comprising:
• a staircase structure having steps at the levels of volatile memory cells;
• and
• conductive contact structures in contact with at least some of the steps of the staircase structure;
• and
• a second structure attached to the first structure through oxide-to-oxide bonding, the second structure comprising:
• a sense amplifier region horizontally overlapping the array region of the first structure and comprising sense amplifier circuitry coupled to the conductive pillars within the array region of the first structure;
• and
• a sub-word line driver region horizontally offset from the sense amplifier region and comprising sub-word line driver circuitry coupled to the conductive contact structures within the conductive contact region of the first structure.

An electronic system, comprising:

• a processor device operably coupled to an input device and an output device;
• and
• a 3D dynamic random-access memory (DRAM) device operably coupled to the processor device and comprising:
• an array structure comprising:
• levels of DRAM cells vertically stacked relative to one another, the DRAM cells of each of the levels comprising:
• access transistors respectively comprising a source region, a drain region, a channel region interposed between the source region and the drain region in a first horizontal direction, gate electrode overlying the channel region and extending in a second horizontal direction orthogonal to the first horizontal direction;
• and
• capacitors neighboring the access transistors in the first horizontal direction, the capacitors respectively vertically overlapping and coupled to the drain region of one of the access transistors;
• and
• conductive digit line structures vertically extending completely through the levels of DRAM cells, the conductive digit line structures coupled to the source region of respective ones of the access transistors of the DRAM cells within the levels of DRAM cells;
• and
• a control circuitry structure attached to the array structure through oxide-to-oxide bonding and comprising sense amplifier circuitry vertically overlying, horizontally overlapping, and coupled to the conductive digit line structures.