Three-dimensional stacked fan-out packaging structure and method making the same

A method for making a three-dimensional stacked fan-out packaging structure, comprising:

• providing a first supporting substrate;
• disposing a separation layer on the first supporting substrate;
• forming a second rewiring layer on the separation layer;
• forming a metal connection pillar on the second rewiring layer, wherein the metal connection pillar is electrically connected to the second rewiring layer;
• providing a first semiconductor chip and bonding the first semiconductor chip to the second rewiring layer;
• forming a first packaging material layer on a surface of the second rewiring layer, wherein the first packaging material layer fills a gap between the first semiconductor chip and the metal connecting pillar and packages the first semiconductor chip and the metal connecting pillar, wherein the first packaging material layer includes a first surface and a second surface opposite to the first surface, wherein the second surface of the first packaging material layer is in contact with the second rewiring layer, and the first surface of the first packaging material layer exposes the metal connecting pillar;
• forming a first rewiring layer on the first surface of the first packaging material layer, wherein the first rewiring layer is electrically connected to the first semiconductor chip and the metal connecting pillar;
• forming a solder bump on a surface of the first rewiring layer away from the first semiconductor chip, wherein the solder bump is electrically connected to the first rewiring layer;
• providing a second supporting substrate and bonding the second supporting substrate to the first rewiring layer;
• removing the first supporting substrate and the separation layer to expose the second rewiring layer;
• providing a second semiconductor chip and electrically connecting the second semiconductor chip to the second rewiring layer;
• forming an underfill layer between the second semiconductor chip and the second rewiring layer;
• forming a second packaging material layer on a periphery area of the second semiconductor chip;
• and
• removing the second supporting substrate.