Graphene-assisted low-resistance interconnect structures and methods of formation thereof

A semiconductor structure, comprising:

• a first conductive feature disposed in a first dielectric layer;
• a second conductive feature disposed in the first dielectric layer and adjacent to the first conductive feature;
• a selective metal capping layer disposed over the first and the second conductive features;
• a graphene layer disposed over the selective metal capping layer;
• a selective etch stop layer (ESL) disposed over the first dielectric layer, wherein sidewalls of the selective ESL directly contacts sidewalls of the selective metal capping layer and the graphene layer;
• a continuous ESL disposed over the selective ESL and over the graphene layer, wherein the continuous ESL and the selective ESL include different materials;
• and
• a via electrically coupled to the first conductive feature by directly landing on the selective metal capping layer.

A semiconductor structure, comprising:

• a first conductive feature disposed in a first dielectric layer;
• a second conductive feature disposed in the first dielectric layer and adjacent to the first conductive feature;
• a graphene layer disposed over the first and the second conductive features;
• a selective metal capping layer disposed over the graphene layer;
• a selective etch stop layer (ESL) disposed over the first dielectric layer, wherein sidewalls of the selective ESL directly contacts sidewalls of the graphene layer and the selective metal capping layer;
• and
• a via electrically coupled to the first conductive feature by directly landing on the graphene layer.