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US 12,113,015 B2Granted
Vertical transistor fuse latches
AssigneeMicron Technology, Inc.
InventorsFatma Arzum Simsek-Ege, Yuan He
Life of this patent
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Abstract
Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.
Claims19
An apparatus, comprising:
- a substrate;
- a memory array coupled with the substrate;
- and
- a latch configured to store information from a fuse for the memory array, the latch disposed within an additional substrate above the substrate and comprising:
- a plurality of p-type vertical transistors comprising a first plurality of gate terminals coupled together;
- and
- a plurality of n-type vertical transistors comprising a second plurality of gate terminals coupled together.
4 more elements
An apparatus, comprising:
- a substrate;
- a memory array coupled with the substrate;
- a latch configured to store information from a fuse for the memory array, the latch comprising a plurality of p-type vertical transistors and a plurality of n-type vertical transistors each at least partially disposed within an additional substrate above the substrate;
- a first plurality of conductive lines, wherein each conductive line in the first plurality of conductive lines couples source terminals of a respective set of the plurality of p-type vertical transistors that are connected in parallel;
- and
- a second plurality of conductive lines, wherein each conductive line in the second plurality of conductive lines couples drain terminals of a respective set of the plurality of n-type vertical transistors that are connective in parallel.
3 more elements
An apparatus, comprising:
- a memory array coupled with a substrate;
- a fuse for the memory array;
- and
- a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising:
- a first p-type vertical transistor comprising a gate terminal and a drain terminal;
- a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor;
- a second p-type vertical transistor comprising a gate terminal and a drain terminal;
- and
- a second n-type vertical transistor comprising:
- a gate terminal coupled with the gate terminal of the second p-type vertical transistor, coupled with the drain terminal of the first p-type vertical transistor, and coupled with the source terminal of the first n-type vertical transistor;
- and
- a source terminal coupled with the drain terminal of the second p-type vertical transistor.
9 more elements
An apparatus, comprising:
- a memory array coupled with a substrate;
- a fuse for the memory array;
- a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising:
- a first p-type vertical transistor comprising a gate terminal and a drain terminal;
- a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor;
- a second p-type vertical transistor comprising a gate terminal and a drain terminal;
- a second n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the second p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the second p-type vertical transistor;
- and
- a network of conductive lines that couples the first p-type vertical transistor, the first n-type vertical transistor, the second p-type vertical transistor, and the second n-type vertical transistor, wherein the network of conductive lines extends through the additional substrate in a three-dimensional manner;
- and
- a set of transistors coupled with the substrate and configured to selectively couple the fuse with respective gate terminals of the first p-type vertical transistor and the first n-type vertical transistor.
8 more elements
An apparatus, comprising:
- a memory array coupled with a substrate;
- a fuse for the memory array;
- a latch at least partially within an additional substrate above the substrate and configured to store information from the fuse, the latch comprising:
- a first p-type vertical transistor comprising a gate terminal and a drain terminal;
- a first n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the first p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the first p-type vertical transistor;
- a second p-type vertical transistor comprising a gate terminal and a drain terminal;
- and
- a second n-type vertical transistor comprising a gate terminal coupled with the gate terminal of the second p-type vertical transistor and comprising a source terminal coupled with the drain terminal of the second p-type vertical transistor;
- a first negative voltage supply coupled with a drain terminal of the first n-type vertical transistor and second negative voltage supply coupled with a drain terminal of the second n-type vertical transistor;
- and
- a first positive voltage supply coupled with a source terminal of the first p-type vertical transistor and second positive voltage supply coupled with a source terminal of the second p-type vertical transistor.
8 more elements
An apparatus, comprising:
- a first substrate;
- a memory array coupled with and disposed at least partially above the first substrate;
- a first p-type vertical transistor of a latch that is configured to store information from a fuse for the memory array, the first p-type vertical transistor at least partially within a second substrate that is above the first substrate;
- a first n-type vertical transistor of the latch, the first n-type vertical transistor at least partially within the second substrate that is above the first substrate;
- and
- a second n-type vertical transistor comprising a gate terminal coupled with a drain terminal of the first p-type vertical transistor and coupled with a source terminal of the first n-type vertical transistor.
3 more elements
Dependencies are inferred from the claim text.