Micro through-silicon via for transistor density scaling

An integrated circuit (IC) package, comprising:

• a package substrate;
• a first die coupled to the package substrate, the first die comprising:
• a silicon substrate having an active device layer and a backside surface opposite the active device layer, the active device layer closer to the package substrate than the backside surface;
• a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
• a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer;
• and
• a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer;
• a bump above an interconnect of the uppermost metal layer, the bump between the first die and the package substrate;
• and
• a second die conductively coupled to the first die, wherein the first die is between the second die and the package substrate.

An integrated circuit (IC) package, comprising:

• a package substrate;
• a base die coupled to the package substrate without an intervening die between the base die and the package substrate, the base die comprising:
• a silicon substrate having an active device layer and a backside surface opposite the active device layer;
• a plurality of metal layers above the active device layer, the plurality of metal layers comprising an uppermost metal layer, a second to uppermost metal layer below the uppermost layer, a third to uppermost metal layer below the second to uppermost metal layer, and a fourth to uppermost metal layer below the third to uppermost metal layer;
• a through silicon via (TSV) extending through the silicon substrate, through the active device layer, and through the fourth to uppermost metal layer, the TSV having a top surface below the third to uppermost metal layer;
• and
• a via between and in contact with the top surface of the TSV and an interconnect of the third to uppermost metal layer;
• a bump above an interconnect of the uppermost metal layer;
• and
• a die conductively coupled to the base die, wherein the base die is between the die and the package substrate.