System on wafer assembly structure and assembly method thereof

A system on wafer assembly structure, comprising:

• a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, each arranged with a bonding region, a testing region and an alignment region, respectively;
• wherein a wafer micro bump array, at least two interconnected wafer test pads and at least one first alignment pad are formed on a side of the wafer layer close to the dielectric layer, and a bonding region, a testing region and an alignment region are formed in regions where the wafer micro bump array, the interconnected wafer test pads and the first alignment pad are located, respectively;
• the dielectric layer is formed with at least one first alignment hole, corresponding to the first alignment pad, configured for preliminary alignment between the wafer layer and the dielectric layer, and at least two conductive members penetrating through a surface of the dielectric layer, corresponding to the interconnected wafer test pads, respectively, configured for an electrical conduction test after the preliminary alignment between the wafer layer and the dielectric layer to test an alignment state;
• the dielectric layer further comprises a plurality of contacts penetrating through the surface of the dielectric layer, the wafer micro bump array is arranged opposite to one side of the contacts close to the wafer layer, and at least one second alignment pad is formed on the other side of the dielectric layer far away from the wafer layer;
• at least one second alignment hole is formed on the circuit board layer, and the second alignment hole corresponds to the second alignment pad and is configured for preliminary alignment between the dielectric layer and the circuit board layer;
• the circuit board layer is formed with at least two pairs of circuit board conduction pads and circuit board test pads electrically connected with each other, arranged on one side of the circuit board layer close to the dielectric layer and the other side of the circuit board layer far away from the dielectric layer, respectively;
• the circuit board test pads corresponds to the conductive members, respectively, and are configured for the electrical conduction test after the preliminary alignment between the dielectric layer and the circuit board layer to test the alignment state;
• and a circuit board micro bump array is formed on the side of the circuit board layer close to the dielectric layer and arranged opposite to the contacts;
• a first assembly arranged on one side of the wafer layer far away from the dielectric layer, wherein the first assembly comprises a bearing portion detachably connected with the wafer layer and at least one latch portion connected with each other;
• and
• a second assembly at least partially arranged around the first assembly, wherein the second assembly comprises a hole portion for accommodating the latch portion, an inner diameter of the hole portion is larger than an outer diameter of the latch portion, there is a gap between one side of the second assembly close to the bearing portion and the bearing portion, and the second assembly is detachably connected with the dielectric layer and the circuit board layer, respectively.