Semiconductor device with tunable epitaxy structures and method of forming the same

A device comprising:

• a first stack of first semiconductor layers disposed over a substrate, wherein each of the first semiconductor layers of the first stack are separated from each other;
• a second stack of second semiconductor layers disposed over the substrate, wherein each of the second semiconductor layers of the second stack are separated from each other;
• a first gate structure wrapping around each of the first semiconductor layers of the first stack;
• a second gate structure wrapping around each of the second semiconductor layers of the second stack;
• a first source/drain feature extending through the first stack of first semiconductor layer to a first depth, the first source/drain feature including a first epitaxial layer and a second epitaxial layer disposed on the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer both include a p-type dopant;
• and
• a second source/drain feature extending through the second stack of second semiconductor layers to a second depth, the second source/drain feature including a third epitaxial layer and a fourth epitaxial layer disposed on the third epitaxial layer, wherein a first ratio of a height of the first epitaxial layer to the first depth of the first source/drain is greater than a second ratio of a height of the third epitaxial layer to the second depth of the second source/drain feature, wherein the third epitaxial layer and the fourth epitaxial layer both include an n-type dopant.

A semiconductor device comprising:

• a first semiconductor fin over a first region of a substrate and a second semiconductor fin over a second region of the substrate;
• a first metal gate structure over the first semiconductor fin and a second metal gate structure over the second semiconductor fin;
• a first spacer along a sidewall of the first metal gate structure and a second spacer along a sidewall of the second metal gate structure;
• and
• a first epitaxial feature over the first semiconductor fin and a second epitaxial feature over the second semiconductor fin, wherein the first epitaxial feature includes a first epitaxial layer and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial feature includes a third epitaxial layer and a fourth epitaxial layer formed over the third epitaxial layer, and a first ratio of a height of the second epitaxial layer to a height of the first epitaxial feature is less than a second ratio of a height of the fourth epitaxial layer to a height of the third epitaxial feature, wherein the first epitaxial layer includes a p-type dopant and the third epitaxial layer and the fourth epitaxial layer both include an n-type dopant.