Reducing spacing between conductive features through implantation

A structure comprising:

• a gate stack;
• a source/drain region aside of the gate stack;
• a silicide region over and contacting the source/drain region;
• an inter-layer dielectric;
• a source/drain contact plug over and contacting the silicide region, with the source/drain contact plug comprising a part in the inter-layer dielectric;
• an etch stop layer over and contacting the source/drain contact plug and the inter-layer dielectric;
• and
• a dopant having a first dopant concentration in a top portion of the inter-layer dielectric, and a second dopant concentration in a bottom portion of the inter-layer dielectric, wherein the first dopant concentration is higher than the second dopant concentration, and wherein the dopant has:
• a first peak concentration at a location between the top portion and the bottom portion;
• and
• a second peak concentration at an interface between the source/drain contact plug and the etch stop layer, and wherein the second peak concentration is higher than the first peak concentration.

A structure comprising:

• an inter-layer dielectric, wherein the inter-layer dielectric comprises:
• a first upper portion comprising a dopant having a first dopant concentration;
• and
• a first lower portion comprising the dopant having a second dopant concentration, wherein the second dopant concentration is smaller than the first dopant concentration;
• a source/drain contact plug in the inter-layer dielectric, wherein the source/drain contact plug comprises a sidewall comprises:
• a second upper portion comprising the dopant having a third dopant concentration;
• and
• a second lower portion comprising the dopant having a fourth dopant concentration, wherein the fourth dopant concentration is smaller than the third dopant concentration;
• a gate stack on a side of the source/drain contact plug;
• and
• a gate contact plug over and electrically coupling to the gate stack.