US 12,112,975 B2Granted

Mechanism for finFET well doping

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann

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Abstract

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

Claims20

Dependent claims

A device comprising:

a first fin extending from a major surface of a substrate, the first fin having a p-type well region and having a p-type channel region over the p-type well region, the p-type well region and a first region of the substrate comprising p-type dopants at a first concentration, the p-type channel region comprising p-type dopants at a second concentration, the second concentration being less than the first concentration, the first region of the substrate extending below the major surface of the substrate to a first depth;
a second fin extending from the major surface of the substrate, the second fin having an n-type well region and having an n-type channel region over the n-type well region, the n-type well region and a second region of the substrate comprising n-type dopants at a third concentration, the n-type channel region comprising n-type dopants at a fourth concentration, the fourth concentration being less than the third concentration, the second region of the substrate extending below the major surface of the substrate to a second depth, the first depth being different from the second depth;
and
an isolation structure surrounding the p-type well region and the n-type well region, the p-type channel region and the n-type channel region protruding above a top surface of the isolation structure.

1 more element

A device comprising:

a first fin extending from a first region of a substrate, the first fin having a first well region and having a first channel region over the first well region, the first well region and the first region of the substrate comprising first majority carriers at a first concentration, the first channel region comprising the first majority carriers at a second concentration, the second concentration being less than the first concentration, the first region of the substrate extending below a top surface of the substrate to a first depth;
and
a second fin extending from a second region of the substrate, the second fin having a second well region and having a second channel region over the second well region, the second well region and the second region of the substrate comprising second majority carriers at a third concentration, the second channel region comprising the second majority carriers at a fourth concentration, the fourth concentration being less than the third concentration, the second region of the substrate extending below the top surface of the substrate to a second depth, the first depth being different from the second depth.

Dependencies are inferred from the claim text.

Facts

Application: 18/346,622Filed 3 Jul 2023 · continuation
Priority: 20 Dec 2013
Published: US 2023/0343634 A126 Oct 2023
Granted: 8 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification40 codes

H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps

Family

Application14/137,690Parent of this division · filed 20 Dec 2013
Application15/213,064Parent of this continuation · filed 18 Jul 2016
US 9,406,546 B2Parent of this division · filed 2 Aug 2016
Application16/417,156Parent of this continuation · filed 20 May 2019
US 10,297,492 B2Parent of this continuation · filed 21 May 2019
Application17/384,994Parent of this continuation · filed 26 Jul 2021
US 11,075,108 B2Parent of this continuation · filed 27 Jul 2021
US 2023/0343634 A1Pre-grant publication · published 26 Oct 2023
US 11,742,237 B2Parent of this continuation
Application15/213,064Parent of this division
US 2015/0179503 A1Published application
US 2016/0329331 A1Published application
US 2019/0273014 A1Published application
US 2021/0358799 A1Published application
US 12,112,975 B2This patent

From the US filing history. Foreign family members aren’t listed.

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