Chip interconnection package structure and method

A chip interconnection package method, wherein the method comprises:

• forming a sacrificial pattern layer on one side surface of a support structure;
• forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer has an interconnection winding pattern which is corresponding to a sacrificial pattern of the sacrificial pattern layer in terms of position;
• forming a first insulating layer on the interconnection winding pattern layer;
• forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in terms of position;
• and
• removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, wherein the first interconnection hole is aligned and communicated with a first interconnection pin of one chip of the plurality of chips which is corresponding in projection position.