Semiconductor device with protection layer and method for fabricating the same

A semiconductor device, comprising:

• a substrate;
• a first gate stack positioned on the substrate and comprising:
• a first gate dielectric layer positioned on the substrate;
• a first gate protection layer positioned on the first gate dielectric layer and comprising titanium silicon nitride;
• a first work function layer positioned on the first gate protection layer;
• a first gate filler layer positioned on the first work function layer, wherein a thickness of the first gate filler layer is larger than a thickness of the first gate dielectric layer;
• a first gate barrier layer positioned between the first work function layer and the first gate filler layer, wherein a bottom side of the first gate barrier layer is in direct contact with a top side of the first work function layer while a top side of the first gate barrier layer is in direct contact with a bottom side of the first gate filler layer;
• a first gate capping layer positioned on the first gate filler layer, wherein a bottom side of the first gate capping layer is in contact with a top side of the first gate filler layer, wherein a thickness of the first gate capping layer is smaller than the thickness of the first gate filler layer;
• and
• a first spacer layer disposed on two sidewalls of the first gate stack, wherein a bottom side of the first spacer layer is in contact with a top side of the substrate and a top end of the first spacer layer is coplanar with a top side of the first gate capping layer, wherein a width of the top end of the first spacer layer is smaller than a width of the bottom side of the first spacer layer;
• an interfacial layer which has a bottom side in contact with the top side of the substrate and a top side in contact with the first gate dielectric layer, wherein the interfacial layer is formed of a chemical oxide of the substrate, wherein the substrate comprises an array area and a peripheral area surrounding the array area, and the first gate stack is positioned on the peripheral area of the first gate dielectric layer;
• and
• an adjustment layer which has a bottom side in contact with the first gate protection layer and a top side in contact with the first work function layer for fine-tuning a threshold voltage of the first gate stack, wherein the first gate barrier layer comprises titanium nitride, or titanium/titanium nitride bi-layer.