Dual reverse pulse sputtering system

A non-transitory memory including non-transitory instructions that are at least one of executable by a processor to execute a method and accessible by a field programmable gate array to configure the field programmable gate array to execute the method, the method comprising:

• causing a first power source to apply a first voltage between first power lead and a second power lead, the first voltage at the first power lead alternates between positive and negative relative to the second power lead in a plasma chamber over multiple cycles;
• causing a second power source to apply a second voltage between a third power lead and the second power lead, the second voltage at the third power lead alternates between positive and negative relative to the second power lead over the multiple cycles;
• and
• causing the first power source and the second power source to phase-synchronize the first voltage with the second voltage, so both, the first voltage and the second voltage are simultaneously negative and simultaneously positive relative to the second power lead over the multiple cycles, wherein the voltages at the first power lead and the third power lead relative to the second power lead are negative at least 70 percent of a time over the multiple cycles.

A pulsed power sputtering system, comprising:

• a plasma chamber enclosing at least a first electrode, a second electrode, and a third electrode;
• means for applying a first voltage at the first electrode that alternates between positive and negative relative to the second electrode during each of multiple cycles;
• means for applying a second voltage to the third electrode that alternates between positive and negative relative to the second electrode during each of the multiple cycles;
• and
• means for phase-synchronizing the first voltage with the second voltage, so both, the first voltage and the second voltage are simultaneously negative during a portion of each cycle and simultaneously positive relative to the second electrode during another portion of each cycle, wherein the first voltage and the third voltage are simultaneously negative relative to the second electrode at least 70 percent of a time over the multiple cycles.