Methods for memory power management and memory devices and systems employing the same

A memory module, comprising:

• a memory device;
• and
• a registering clock driver (RCD) coupled to the memory device and configured to:
• receive an indication of a duration corresponding to enabling an input buffer of the memory device;
• receive an enable signal and a command/address signal at a first time,
• send the enable signal to the memory device at a second time subsequent to the first time, and
• send the command/address signal to the memory device at a third time subsequent to the second time by a delay corresponding to the duration,
• wherein the memory device is configured to:
• reduce, in response to the RCD receiving the indication of the duration, a programmable latency of the memory device by an amount corresponding to the duration;
• and
• enable a disabled input buffer in response to detecting the enable signal.

A memory device, comprising:

• an input buffer;
• and
• circuitry coupled to the input buffer and configured to:
• reduce a programmable latency of the memory device by an amount corresponding to a duration that corresponds to enabling the input buffer;
• disable the input buffer in response to a determination that the memory device is idle;
• re-enable the input buffer in response to detecting an enable signal received at the memory device at a first time;
• and
• receive a command/address signal at a second time subsequent to the first time by a delay corresponding to the duration.