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US 12,112,829 B2Granted
Memory array circuits, memory structures, and methods for fabricating a memory array circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Ying Lee, Chia-En Huang, Meng-Sheng Chang
Life of this patent
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Abstract
A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.
Claims20
A memory array circuit, comprising:
- a first memory array, including:
- a first set of memory cells located in an inner area of the first memory array;
- and
- a second set of memory cells located along an edge of the first memory array, wherein a first channel length of a first transistor in the first set of memory cells is less than a second channel length of a second transistor in the second set of memory cells;
- and
- a set of dummy cells surrounding the first memory array, wherein each dummy cell includes one or more active regions and a plurality of gate structures over the one or more active regions, wherein the gate structures in the dummy cells and gate structures of the memory cells have the same width.
3 more elements
A memory structure, comprising:
- a plurality of memory cells forming a memory array, wherein a first channel length of a first transistor in a first set of memory cells located in an inner area of the memory array is less than a second channel length of a second transistor in a second set of memory cells located along an edge of the memory array, at least one of the memory cells comprising:
- a plurality of active regions extending in a first direction;
- and
- a plurality of gate structures disposed over the plurality of active regions and extending in a second direction;
- and
- a plurality of dummy cells surrounding the memory array, at least one of the dummy cells comprising:
- one or more dummy active regions extending in the first direction;
- and
- a plurality of dummy gate structures disposed over the one or more active regions and extending in the second direction, wherein the dummy gate structures and the gate structures of the memory cells have the same width.
6 more elements
A method for fabricating a memory array circuit, the method comprising:
- forming a plurality of memory cells of a first memory array, wherein a first channel length of a first transistor in a first set of memory cells located in an inner area of the first memory array is less than a second channel length of a second transistor in a second set of memory cells located along an edge of the first memory array;
- and
- forming a plurality of dummy cells surrounding the first memory array, by providing one or more active regions and a plurality of gate structures, wherein each of the dummy cells includes the one or more active regions and the plurality of gate structures over the one or more active regions, wherein the gate structures in the dummy cells and the gate structures in the memory cells have the same width.
Dependencies are inferred from the claim text.