Method and system for repairing faulty cells of memory device

A system for repairing a memory device comprising:

• one or more processors and a memory that includes one or more faulty memory cells, wherein the one or more processors are configured to:
• detect one or more faulty memory cells that are faulty in a memory device and a location corresponding to the each of one or more faulty memory cells;
• define a Redundancy Analysis (RA) environment, comprising the detected location of the each of one or more faulty memory cells and a plurality of spare rows (SRs) and a plurality of spare columns (SCs), for repairing the memory device;
• repair each of the one or more faulty memory cells based on an RA training process using the defined RA environment and mapping of the detected location of each of the one or more faulty memory cells with the plurality of SRs or SCs;
• determine whether at least one faulty memory cell among the one or more faulty memory cells is left unrepaired after the repairing of the one or more faulty memory cells;
• determine whether any SR or SC among the plurality of SRs or SCs is remaining based on the determination that the least one faulty memory cell among the one or more faulty memory cells is left unrepaired;
• and
• train, based on the determination that indicates the at least one faulty memory cell is left unrepaired and at least one SR or SC is remaining, a first neural network (NN) such that the first NN performs an action for repairing of the one or momre faulty memory cells,
• wherein the action is performed such that a maximum number of one or more faulty memory cells is reparable and a minimum number of SRs and SCs are utilized during the repairing.