Scan chain compression for testing memory of a system on a chip

A system for testing a memory of a chip, the system comprising:

• a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, the first n-bit compression structure being configured to receive, in a capture stage, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one,
• wherein the first n-bit compression structure further includes compression logic and a second stage latch, such that, in the capture stage, the values are passed from each respective first stage latch through the compression logic to output a single compressed address value and the single compressed address value is provided to the second stage latch.

A non-transitory computer readable medium comprising stored instructions for testing a memory of a chip, the instructions, when executed by a processor, causing the processor to:

• in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one;
• and
• in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.