Power leakage blocking in low-dropout regulator

A circuit, comprising:

• a low-dropout regulator comprising a first transistor, wherein the low-dropout regulator is configured to output a second voltage based on a first voltage;
• a pair of transistors comprising a second transistor and a third transistor, wherein respective bulks of the pair of transistors are connected to a bulk of the first transistor;
• and
• a control circuit connected to gates of the pair of transistors, wherein the control circuit is configured to output signals to the gates of the pair of transistors, the control circuit comprises a resistor, and a first terminal of the resistor is connected to a reference voltage.

A memory device, comprising:

• a memory array for storing data;
• and
• a peripheral circuit coupled to the memory array and comprising a voltage generation circuit, the voltage generation circuit comprising:
• an amplifier;
• a first transistor;
• wherein a gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier;
• a second transistor, wherein a first terminal of the second transistor connected to a second terminal of the first transistor;
• a third transistor, wherein a first terminal of the third transistor is connected to the first terminal of the second transistor, and a second terminal of the third transistor is connected to a second terminal of the first transistor;
• a signal pair generation circuit connected to a gate terminal of the second transistor and a gate terminal of the third transistor;
• and
• a leakage track bias generator circuit connected to the signal pair generation circuit, wherein the leakage track bias generator circuit comprises a resistor, and a first terminal of the resistor is connected to a reference voltage.