Read voltage calibration method, memory storage device, and memory control circuit unit

A memory storage device, comprising:

• a connection interface unit, used to couple to a host system;
• a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units;
• and
• a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory control circuit unit is configured to:
• send a plurality of first read command sequences, wherein the first read command sequences are configured to instruct to read data from a first physical unit among the physical units by using a plurality of read voltage levels;
• decode the data to obtain a plurality of error evaluation parameters, wherein the error evaluation parameters respectively correspond to one of the read voltage levels;
• determine a first vector distance parameter according to a first error evaluation parameter among the plurality of error evaluation parameters, wherein the first error evaluation parameter corresponds to a first read voltage level among the read voltage levels;
• determine a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level;
• determine a target read voltage level according to one of the candidate read voltage levels;
• and
• send a second read command sequence, wherein the second read command sequence is configured to instruct to read the data again from the first physical unit by using the target read voltage level.

A memory control circuit unit, configured to control a rewritable non-volatile memory module, the memory control circuit unit comprising:

• a host interface, configured to couple to a host system;
• a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units;
• an error detection and calibration circuit;
• and
• a memory management circuit, coupled to the host interface, the memory interface, and the error detection and calibration circuit,
• wherein the memory management circuit is configured to:
• send a plurality of first read command sequences, wherein the first read command sequences are configured to instruct to read data from a first physical unit among the physical units by using a plurality of read voltage levels;
• instruct the error detection and calibration circuit to decode the data to obtain a plurality of error evaluation parameters, wherein the error evaluation parameters respectively correspond to one of the read voltage levels;
• determine a first vector distance parameter according to a first error evaluation parameter among the plurality of error evaluation parameters, wherein the first error evaluation parameter corresponds to a first read voltage level among the read voltage levels;
• determine a plurality of candidate read voltage levels according to the first vector distance parameter and the first read voltage level;
• determine a target read voltage level according to one of the candidate read voltage levels;
• and
• send a second read command sequence, wherein the second read command sequence is configured to instruct to read the data again from the first physical unit by using the target read voltage level.