Apparatus containing memory array structures having multiple sub-blocks

An apparatus, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a data line;
• a plurality of sets of field-effect transistors, wherein each set of field-effect transistors of the plurality of sets of field-effect transistors is between the data line and a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein each set of field-effect transistors of the plurality of sets of field-effect transistors has N field-effect transistors connected in series, and wherein each set of field-effect transistors of the plurality of sets of field-effect transistors was fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions;
• and
• N select lines, wherein each select line of the N select lines is connected to a control gate of a respective field-effect transistor of each set of field-effect transistors of the plurality of sets of field-effect transistors corresponding to a same position of the plurality of possible binary permutations of two threshold voltages.

An apparatus, comprising:

• an array of memory cells comprising a plurality of strings of series-connected memory cells;
• a first data line;
• a second data line;
• a first plurality of sets of field-effect transistors, wherein each set of field-effect transistors of the first plurality of sets of field-effect transistors is between the first data line and a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein each set of field-effect transistors of the first plurality of sets of field-effect transistors has N field-effect transistors connected in series, and wherein each set of field-effect transistors of the first plurality of sets of field-effect transistors was fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions;
• a second plurality of sets of field-effect transistors, wherein each set of field-effect transistors of the second plurality of sets of field-effect transistors is between the second data line and a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, wherein each set of field-effect transistors of the second plurality of sets of field-effect transistors has N field-effect transistors connected in series, and wherein each set of field-effect transistors of the second plurality of sets of field-effect transistors was fabricated to have a respective binary permutation of two threshold voltages of the plurality of possible binary permutations of two threshold voltages having N positions;
• and
• N select lines, wherein N is an integer value greater than or equal to one, and wherein each select line of the N select lines is connected to a control gate of a respective field-effect transistor of each set of field-effect transistors of the first plurality of sets of field-effect transistors and a respective field-effect transistor of each set of field-effect transistors of the second plurality of sets of field-effect transistors corresponding to a same position of the plurality of possible binary permutations of two threshold voltages.