Memory device, the operation method thereof and memory system

A memory system, comprising one or more memory devices and a memory controller coupled to and configured to control the one or more memory devices, wherein each of the memory devices comprises a memory cell array and a peripheral circuit coupled to the memory cell array;

• the memory cell array comprises a plurality of memory planes;
• the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;
• the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits;
• the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;
• during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits;
• and
• during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.

A method for operating a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array;

• the memory cell array comprises a plurality of memory planes;
• the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane;
• and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;
• the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits;
• the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;
• the method comprises:
• receiving a first instruction, wherein the first instruction is configured to simultaneously perform a program operation on the plurality of memory planes;
• applying a plurality of different voltages output by the plurality of selected voltage selection circuits to each memory plane in response to the first instruction;
• receiving a second instruction, wherein the second instruction is configured to perform a read operation on the plurality of memory planes;
• and
• applying a part of the plurality of different voltages output by the plurality of selected voltage selection circuits respectively to different memory planes in response to the second instruction.