High speed multi-level cell (MLC) programming in non-volatile memory structures
AssigneeSanDisk Technologies LLC
InventorsXiang Yang, Deepanshu Dutta, Muhammad Masuduzzaman, Jiacen Guo
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Abstract
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
Claims20
A method for programming a memory array of a non-volatile memory structure, comprising:
- initiating a programming operation with respect to a population of MLC type memory cells, wherein the programming operation comprises programming:
- a first programmable state according to a first programming voltage;
- a second programmable state according to a second programming voltage;
- and
- a third programmable state according to a third programming voltage, wherein (i) a magnitude of the second programming voltage is greater than a magnitude of the first programming voltage, and (ii) a magnitude of the third programming voltage is greater than the magnitude of the second programming voltage;
- in a first program pulse, programming one or more selected memory cells from an erased data state to the first programmable state and programming one or more selected memory cells to the second programmable state;
- and
- in a second program pulse, programming one or more selected memory cells according to the third programmable state.
A method for programming a memory array of a non-volatile memory structure, comprising:
- initiating a programming operation with respect to a population of MLC type memory cells, wherein the programming operation comprises programming:
- a first programmable state according to a first programming voltage;
- a second programmable state according to a second programming voltage;
- and
- a third programmable state according to a third programming voltage, wherein (i) a magnitude of the second programming voltage is greater than a magnitude of the first programming voltage, and (ii) a magnitude of the third programming voltage is greater than the magnitude of the second programming voltage;
- and
- in a single program pulse, programming one or more selected memory cells from an erased state to each of the first programmable state, the second programmable state, and the third programmable state.
A non-volatile memory system, comprising:
- a memory array comprising a population of MLC type memory cells;
- and
- a memory controller coupled to the memory array and:
- in a first program pulse, programming one or more of the memory cells from an erased state to each of:
- a first programmable state according to a first programming voltage;
- and
- a second programmable state according to a second programming voltage;
- and
- in a second program pulse, programming the selected one or more of the memory cells with respect to the first programmable state, wherein (i) a magnitude of the second programming voltage is greater than a magnitude of the first programming voltage, and (ii) a magnitude of the third programming voltage is greater than the magnitude of the second programming voltage.
Dependencies are inferred from the claim text.