Cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory macro and method for edge intelligence

A cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory (CIM) macro for edge intelligence, comprising a SRAM cell and a column-shared reconfigurable Boolean computation cell, and configured to

• perform a reconfiguration computation based on the SRAM cell to obtain a reconfigured structure;
• and
• output, by the column-shared reconfigurable Boolean computation cell, a computation result based on the reconfigured structure, wherein
• the SRAM cell has a plurality of transistors and separates a wordline (WL) to obtain a wordline X (WLX) and a wordline Y (WLY);
• the WLX controls a bitline (BL) to perform reading and writing on the corresponding SRAM cell;
• the WLY controls a bitline bar (BLB) to perform reading and writing on the corresponding SRAM cell;
• a plurality of additional transistors connected to a BL and a BLB in each column are column-shared reconfigurable Boolean computation cells;
• voltage levels of a read wordline PX (RWL_PX) and a read wordline NX (RWL_NX) depend on a mode of a to-be-performed Boolean computation for the BL and an externally input value;
• voltage levels of a read wordline PY (RWL_PY) and a read wordline NY (RWL_NY) depend on the mode of the to-be-performed Boolean computation for the BLB and the externally input value;
• and
• the computation result obtained by the column-shared reconfigurable Boolean computation cell is separately output through a read bitline X (RBL_X) and a read bitline Y (RBL_Y).