Memory device including predecoder and operating method thereof

A memory device comprising:

• a static random-access memory (SRAM) cell connected to a wordline and a bitline;
• a wordline driver configured to provide a wordline voltage having a first voltage to the wordline;
• a bitline precharge circuit configured to provide a bitline voltage having a second voltage, which is lower than the first voltage, to the bitline;
• and
• a wordline predecoder configured to generate a “predec” signal, which is associated with enabling the wordline voltage,
• wherein the wordline predecoder includes
• a first pull-up transistor which is configured to pull up the “predec” signal based on a first control signal having the first voltage,
• a second pull-up transistor, which is configured to pull up the “predec” signal based on a second control signal having the first voltage,
• a first pull-down transistor, which is configured to pull down the “predec” signal based on the second control signal having the second voltage, and
• a second pull-down transistor, which is configured to pull down the “predec” signal based on the first control signal having the first voltage, the pulling up based on the first control signal being concurrent with the pulling down based on the second control signal.

An operating method of a memory device, comprising:

• allowing an internal clock signal to transition from a first level to a second level;
• in response to the internal clock signal transitioning to the second level, allowing a bitline precharge voltage to rise from the first level to the second level at a first time;
• and
• in response to the internal clock signal transitioning to the second level, allowing a wordline voltage to rise from the first level to a third level, which is greater than the second level, at a second time, which is later than the first time.