Back to results
US 12,112,794 B2Granted
Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein
AssigneeR&D 3 LLC
InventorRavindraraj Ramaraju
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
Claims19
A memory cell, comprising:
- multiple data ports, comprising:
- a first data port that is a write port for writing data to be stored in the memory cell;
- and
- a second data port that is a read port having a variable impedance that varies in accordance with a data value stored therein, wherein the data value is one of at least three different data values that the memory cell is capable of storing;
- and
- multiple control ports, comprising:
- a first control port coupled with the write port;
- and
- a second control port coupled with the read port;
- wherein:
- the write port is coupled with a write bit line;
- and
- the read port is coupled between a read bit line and a fixed reference.
10 more elements
A method, comprising:
- storing more than one bit of information in a memory cell, wherein the storing comprises:
- writing, though a write port of the memory cell, a data value corresponding to the more than one bit of information, wherein the write port is first data port of multiple data ports of the memory cell, and wherein the write port is coupled with a first control port of multiple control ports of the memory cell;
- and
- determining the more than one bit of information stored in the memory cell, wherein the determining comprises:
- reading an output of a read port of the memory cell, wherein the read port has an impedance that varies in accordance with, and is indicative of, the data value stored therein, wherein the data value is one of at least three different data values that the memory cell is capable of storing, wherein the read port is a second data port of the multiple data ports of the memory cell, and wherein the read port is coupled with a second control port of the multiple control ports of the memory cell;
- wherein:
- the write port is coupled with a write bit line;
- and
- the read port is coupled between a read bit line and a fixed reference.
6 more elements
Dependencies are inferred from the claim text.