Memory device for wafer-on-wafer formed memory and logic

An apparatus, comprising:

• a plurality of tiles coupled to a global input/output (I/O) bus;
• each tile including a respective array of memory cells configured on a memory die and coupled to sense lines and access lines of the memory die;
• wherein each of a plurality of subsets of the sense lines is coupled to a respective I/O line on the memory die;
• wherein local I/O lines are coupled to a global I/O line on the memory die for communication of data on the memory die via the global I/O bus;
• and
• a respective transceiver associated with the respective local I/O line and a wafer-on-wafer bond, wherein:
• the respective transceiver is configured to enable communication of the data off the memory die via the respective local I/O line in response to receipt of a first signal from a controller;
• and
• the respective transceiver is configured to enable communication of the data off the memory die via the wafer-on-wafer bond in response to receipt of a second signal from the controller.

An apparatus, comprising:

• a plurality of memory dies fabricated on a memory wafer;
• wherein each of the plurality of memory dies includes:
• an array of memory cells;
• a plurality of local input/output lines on the plurality of memory dies for communication of data on the plurality of memory dies;
• a plurality of transceivers associated with the plurality of local input/output lines on the plurality of memory dies, the plurality of transceivers configured to enable communication of data to one or more memory devices off the plurality of memory dies via the local input/output lines;
• and
• memory-to-logic circuitry coupled to the plurality of transceivers and configured to be coupled to a logic die via a wafer-on-wafer bond, wherein:
• each respective transceiver of the plurality of transceivers is configured to enable communication of the data off a respective memory die via a respective local input/output line in response to receipt of a first signal from a controller;
• and
• each respective transceiver of the plurality of transceivers is configured to enable communication of the data off the respective memory die via the wafer-on-wafer bond in response to receipt of a second signal from the controller.

A method, comprising:

• receiving a signal indicative of data at a sense amplifier configured on a memory die and through a sense line of the memory die;
• transferring the signal indicative of data to a multiplexor configured on the memory die coupled to the sense amplifier configured on the memory die;
• receiving a control signal to switch a memory device between:
• a first mode of operation, wherein the first mode of operation configures the memory device for communication of data on the memory die via local input/output lines;
• and
• a second mode of operation, wherein the second mode of operation configures the memory device for communication of data to one or more devices off the memory die via a wafer-on-wafer bond;
• and
• transferring the signal indicative of data from the multiplexor configured on the memory die to circuitry internal to the memory device or circuitry external to the memory device based on whether the memory device is configured in the first mode of operation or the second mode of operation.