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US 12,112,789 B2Granted
Apparatuses and methods for input buffer enable clock synchronization
AssigneeMicron Technology, Inc.
InventorTakayuki Miyamoto
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for input buffer enable clock synchronization. A command shifter receives a command, such as a write command. The command shifter passes the command through latches of the shifter in synchronization with a clock signal. Data buffer enable logic provides a data buffer enable signal with a level based on how long it takes the command to pass through the command shifter. The data buffer enable logic synchronizes changes to the level of the data buffer enable signal to the clock signal.
Claims26
An apparatus comprising:
- data buffer enable logic configured to provide a first intermediate data buffer enable signal and a second intermediate data buffer signal in series responsive to a first command and a second command received in series and output a combined data buffer enable signal when a gap between the first intermediate data buffer enable signal and the second intermediate data buffer enable signal is less than a predetermined period of time wherein the data buffer enable logic comprises:
- a first shifter which includes a plurality of latches in series, each configured to provide one of a plurality of internal command signals;
- and
- a logic gate configured to provide the first and the second intermediate data buffer enable signal based on the plurality of internal command signals.
1 more element
An apparatus comprising:
- a command shifter configured to provide a plurality of internal command signals responsive to a command, the plurality of internal command signals having respective amount of delay each defined as one or multiple number of cycles of a clock signal;
- and
- data buffer enable logic configured to provide a data buffer enable signal based, at least in part, on the plurality of internal command signals, wherein each of rising and falling edges of the data buffer enable signal are synchronized to the clock signal.
An apparatus comprising:
- a first shifter comprising a first plurality of flip-flops, the first shifter configured to receive a command and pass the command through the first plurality of flip-flops in synchronization with a clock signal;
- a logic gate configured to provide an initial data buffer enable signal with a level based on whether the command is in any of the first plurality of flip-flops;
- and
- a second shifter comprising a second plurality of flip-flops, the second shifter configured to receive the initial data buffer enable signal from the logic gate and pass the data buffer enable signal through the second plurality of flip-flops in synchronization with the clock signal to generate a data buffer enable signal.
1 more element
A method comprising:
- passing a command through a command shifter in synchronization with a clock signal;
- determining a level of a data buffer enable signal based on an amount of time the command is passing through the command shifter;
- changing the level of the data buffer enable signal in synchronization with the clock signal;
- activating data input buffer circuits responsive to the data buffer enable signal at an active level;
- and
- receiving data from data terminals when the data input buffer circuits are active.
3 more elements
A method comprising:
- passing a command through a command shifter in synchronization with a clock signal;
- determining a level of a data buffer enable signal based on an amount of time the command is passing through the command shifter;
- changing the level of the data buffer enable signal in synchronization with the clock signal;
- dividing an initial clock signal into a first divided clock signal which is the clock signal and a second divided clock signal;
- and
- passing the command through a second command shifter in synchronization with the second divided clock signal.
3 more elements
A method comprising:
- passing a command through a command shifter in synchronization with a clock signal;
- determining a level of a data buffer enable signal based on an amount of time the command is passing through the command shifter;
- and
- changing the level of the data buffer enable signal in synchronization with the clock signal, wherein the command shifter includes a plurality of latches each configured to provide a respective one of a plurality of internal command signals, the method further comprising setting the data buffer enable signal at an active level based on the plurality of internal command signals.
1 more element
A method comprising:
- passing a command through a command shifter in synchronization with a clock signal;
- determining a level of a data buffer enable signal based on an amount of time the command is passing through the command shifter;
- and
- changing the level of the data buffer enable signal in synchronization with the clock signal;
- receiving the command at a first time;
- receiving a second command at a second time;
- and
- maintaining the level of the data buffer enable signal at the active level if the different between the first time and the second time is less than a predetermined period of time.
5 more elements
Dependencies are inferred from the claim text.