Apparatuses, systems, and methods for configurable memory

A system comprising:

• a memory controller;
• and
• a memory device comprising a reference line and a memory array including at least one configuration device, a plurality of memory cells and at least one sense amplifier,
• wherein the memory controller is configured to provide at least one command to the memory device,
• wherein, based, at least in part, on the at least one command, the memory device is configured to program the at least one configuration device to arrange at least one portion of the memory array in a first arrangement and arrange at least one other portion of the memory array in a second arrangement different from the first arrangement,
• wherein the at least one configuration device connects one memory cell of the plurality of memory cells to a first input of the at least one sense amplifier and further connects the reference potential line to a second input of the at least one sense amplifier in the first arrangement.

A method comprising:

• receiving, at a memory device, a command;
• responsive, at least in part, to the command, programming at least one configuration device of the memory device;
• and
• responsive to the programming, arranging, with the at least one configuration device, a first portion of a memory array of the memory device in a first arrangement and a second portion of the memory array in a second arrangement different from the first arrangement,
• wherein arranging the first portion of the memory array in the first arrangement comprises selectively connecting individual ones of a plurality of memory cells to a plurality of sense amplifiers such that one of the plurality of memory cells is coupled to a corresponding one of the plurality of sense amplifiers at a time and further coupling the plurality of sense amplifiers to a reference potential line.

An apparatus comprising:

• a memory array comprising a first portion arranged in a first arrangement and a second portion of the memory array in a second arrangement, wherein
• the first arrangement comprises individual ones of a first plurality of memory cells coupled to corresponding ones of a first plurality of sense amplifiers, wherein the first plurality of sense amplifiers are configured as unipolar sense amplifiers;
• and
• the second arrangement comprises at least two of a second plurality of memory cells coupled to a sense amplifier a plurality of sense amplifiers, wherein the sense amplifier is configured to act as a differential sense amplifier, wherein the memory array comprises:
• a first side wall;
• a second side wall:
• a third side wall, wherein the first, second, and third side walls are parallel and spaced apart from one another:
• a first plurality of capacitors arranged along the first sidewall;
• a second plurality of capacitors arranged along the second sidewall;
• a third plurality of capacitors arranged along the third side wall.