Pixel drive circuit, driving method, and display panel

A display panel, comprising a plurality of pixel cells arranged in an array;

• wherein each pixel cell is arranged with a pixel drive circuit;
• wherein the pixel drive circuit comprises:
• a light-emitting element;
• a power supply line, comprising a high-potential power supply and a low-potential power supply, connected to the light-emitting element;
• a pulse amplitude modulation unit, comprising a first drive transistor connected to the light-emitting element and the power supply line;
• wherein a driving current with different amplitudes is provided to the light-emitting element according to a voltage applied to a gate of the first drive transistor;
• and
• a pulse width modulation unit, comprising a second drive transistor connected to the light-emitting element and the pulse amplitude modulation unit;
• wherein a duration of the driving current of the light-emitting element is controlled according to a voltage applied to a gate of the second drive transistor;
• wherein the pulse width modulation unit further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor;
• a first pole plate of the first capacitor is connected to the gate of the second drive transistor, and a second pole plate of the first capacitor is connected to the power supply line;
• a source of the first transistor is connected to a first signal line, a drain of the first transistor is connected to the gate of the second drive transistor, and a gate of the first transistor is connected to a first scan control line;
• a source of the second transistor is connected to a second signal line, a drain of the second transistor is connected to the gate of the second drive transistor, and a gate of the second transistor is connected to a drain of the third transistor and to a first pole plate of the second capacitor;
• a source of the third transistor is connected to a third signal line, the drain of the third transistor is connected to the gate of the second transistor and to the first pole plate of the second capacitor, and a gate of the third transistor is connected to a second scan control line;
• a source of the fourth transistor is connected to a control signal line, a drain of the fourth transistor is connected to a second pole plate of the second capacitor, and a gate of the fourth transistor is connected to a third scan control line.