Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

A data processing system comprising:

• a parallel processor comprising:
• a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, wherein the multiple types of compute units include a first sparse compute unit configured for input at a first level of sparsity and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity;
• a plurality of processing resources coupled with the hardware scheduler, the plurality of processing resources including the first sparse compute unit;
• and
• hybrid memory circuitry coupled with the plurality of processing resources, the hybrid memory circuitry including a memory controller, a memory interface, and the second sparse compute unit;
• and
• a memory device coupled with the memory interface of the hybrid memory circuitry.

A method comprising:

• receiving a first instruction for execution at a parallel processor, the parallel processor including a first sparse compute unit configured for input at a first level of sparsity and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity;
• scheduling pipeline commands to enable execution of the first instruction via a hardware scheduler of the parallel processor, the pipeline commands scheduled to the first sparse compute unit;
• receiving a second instruction for execution at the parallel processor;
• and
• scheduling pipeline commands to enable execution of the second instruction via the hardware scheduler of the parallel processor, the pipeline commands scheduled to the second sparse compute unit.