Machine learning accelerator with decision tree interconnects

An apparatus comprising:

• at least one processor;
• at least one memory including instruction code;
• and
• control logic, wherein the control logic comprises:
• a plurality of decision tree unit hardware modules;
• a register;
• a plurality of multiplexers, wherein each multiplexer is coupled to the register, and coupled to a respective decision tree unit hardware module of the plurality of decision tree unit hardware modules;
• and
• a majority voter module coupled to the register and to the plurality of decision tree unit hardware modules;
• wherein each decision tree unit hardware module comprises a decision tree structure, wherein each decision tree structure of the plurality of decision tree unit hardware modules comprises a balanced decision tree structure having a same number of nodes and a same depth, and hard-wired interconnects;
• wherein the at least one memory and the instruction code are configured to, with the at least one processor, to instruct the control logic to:
• cause the register to output control data to the plurality of multiplexers to cause the plurality of multiplexers to selectively configure each of one or more of the decision tree unit hardware modules to function as an independent decision tree structure or to selectively configure at least two of the decision tree unit hardware modules to form a decision tree structure which comprises a combination of at least a first decision tree structure and a second decision tree structure of the plurality of decision tree unit hardware modules by selectively connecting at least one leaf node of the first decision tree structure to an internal node of the second decision tree structure;
• and
• cause the majority voter module to receive output data from the decision tree unit hardware modules, and the control data from the register which indicates the configuration of the decision tree unit hardware modules, and generate a decision based on the received output data and the control data.

A method, comprising:

• training a plurality of decision tree structures each implemented by one of a plurality of decision tree unit hardware modules, wherein each one of the plurality of decision tree structures comprises hard-wired interconnects and is balanced in shape and uniform in shape and has a same number of nodes and a same depth with respect to each other ones of the plurality of decision tree structures;
• setting control data in a register which is coupled to a plurality of multiplexers, each multiplexer being coupled to a respective decision tree unit hardware module of the plurality of decision tree unit hardware modules;
• applying the control data to the plurality of multiplexers to cause the plurality of multiplexers to selectively configure each of one or more of the decision tree unit hardware modules to function as an independent decision tree structure or to selectively configure at least two of the decision tree unit hardware modules to form a decision tree structure which comprises a combination of at least a first decision tree structure and a second decision tree structure by selectively connecting at least one leaf node of the first decision tree structure to an internal node of the second decision tree structure;
• and
• receiving, by a majority voter module, output data from the decision tree unit hardware modules, and the control data from the register which indicates the configuration of the decision tree unit hardware modules, to generate a decision based on the received output data and the control data;
• wherein one or more of the steps are executed by processing circuitry configured to execute instruction code.

An article of manufacture comprising a non-transitory computer-readable storage medium having embodied therein executable instruction code that when executed by a processor causes the processor to perform steps of:

• training a plurality of decision tree structures each implemented by one of a plurality of decision tree unit hardware modules, wherein each one of the plurality of decision tree structures comprises hard-wired interconnects and is balanced in shape and uniform in shape and has a same number of nodes and a same depth with respect to each other ones of the plurality of decision tree structures;
• setting control data in a register which is coupled to a plurality of multiplexers, each multiplexer being coupled to a respective decision tree unit hardware module of the plurality of decision tree unit hardware modules;
• applying the control data to the plurality of multiplexers to cause the plurality of multiplexers to selectively configure each of one or more of the decision tree unit hardware modules to function as an independent decision tree structure or to selectively configure at least two of the decision tree unit hardware modules to form a decision tree structure which comprises a combination of at least a first decision tree structure and a second decision tree structure by selectively connecting at least one leaf node of the first decision tree structure to an internal node of the second decision tree structure;
• and
• receiving, by a majority voter module, output data from the decision tree unit hardware modules, and the control data from the register which indicates the configuration of the decision tree unit hardware modules, to generate a decision based on the received output data and the control data.

A system comprising:

• a plurality of decision tree structures, wherein each one of the plurality of decision tree structures comprises a balanced decision tree structure with hard-wired interconnects and is balanced in shape and uniform in shape and has a same number of nodes and a same depth with respect to each other ones of the plurality of decision tree structures;
• configuration logic operatively coupled to the plurality of decision tree structures, wherein the configuration logic comprises a register, and a plurality of multiplexers, wherein each multiplexer is coupled to the register, and coupled to a respective decision tree structure of the plurality of decision tree structures;
• and
• output generation logic coupled to the register and to the plurality of decision tree structures;
• wherein the register is configured to output control data to the plurality of multiplexers to cause the plurality of multiplexers to selectively configure each of one or more of the decision tree structures to function as an independent decision tree structure or to selectively configure at least two of the decision tree structures to form a decision tree structure which comprises a combination of at least a first decision tree structure and a second decision tree structure of the plurality of decision tree structures by selectively connecting at least one leaf node of the first decision tree structure to an internal node of the second decision tree structure;
• and
• wherein the output generation logic is configured to receive output data from the decision tree structures, and the control data from the register which indicates the configuration of the decision tree structures, and generate a decision based on the received output data and the control data.