Processor with hardware pipeline

A method comprising:

• running software on execution logic, the execution logic comprising one or more execution units;
• writing, by the software, descriptors to a register bank to specify tasks to be processed by a hardware pipeline, wherein the register bank comprises a plurality of register sets, each register set being for holding one of the descriptors of one of the tasks at any one time;
• connecting, by a first selector, the execution logic to a selected one of the register sets at any one time, and thereby enabling the software to write successive ones of said descriptors to different ones of said register sets;
• connecting, by a second selector, the hardware pipeline to a selected one of the register sets at any one time;
• and
• controlling, by control circuitry, the hardware pipeline to begin processing a current one of said tasks based on the descriptor in a current register set of the register sets while the software is writing the descriptor of another of said tasks to another of the register sets, the current register set being that currently connected to the hardware pipeline by the second selector.

A non-transitory computer readable storage medium having stored thereon computer readable code, the computer readable code when executed by a processor performing a method of:

• running software on execution logic, the execution logic comprising one or more execution units;
• writing, by the software, descriptors to a register bank to specify tasks to be processed by a hardware pipeline, wherein the register bank comprises a plurality of register sets, each register set being for holding one of the descriptors of one of the tasks at any one time;
• connecting, by a first selector, the execution logic to a selected one of the register sets at any one time, and thereby enabling the software to write successive ones of said descriptors to different ones of said register sets;
• connecting, by a second selector, the hardware pipeline to a selected one of the register sets at any one time;
• and
• controlling, by control circuitry, the hardware pipeline to begin processing a current one of said tasks based on the descriptor in a current register set of the register sets while the software is writing the descriptor of another of said tasks to another of the register sets, the current register set being that currently connected to the hardware pipeline by the second selector.