US 12,112,178 B2 · Memory-independent and scalable state component initialization for a processor

Abstract

Systems or methods of the present disclosure may provide an initialization technique that enables the initialization of multiple states in an efficient manner. The initialization technique includes a register to track usage of state components of the processor and a decode unit to decode a state initialization instruction. The state initialization instruction indicates that of the state components are to be initialized. The initialization technique also includes an execution unit coupled with the decode unit. The execution unit, in response to the state initialization instruction, is to initialize the state components without reading another state component from memory as part of the initialization.

Claims17

Dependent claims

A processor comprising:

a register to track usage of state components of the processor;
a decode unit to:
decode a state initialization instruction, wherein the state initialization instruction indicates that the state components are to be initialized by zeroing out the state components;
and
determine whether a current privilege exceeds a privilege threshold and set a bit mask based at least in part on the current privilege exceeding the privilege threshold;
and
an execution unit coupled with the decode unit, wherein the execution unit, in response to the state initialization instruction, is to initialize the state components based on the bit mask and without reading another state component from memory as part of the initialization.

4 more elements

Dependencies are inferred from the claim text.

Memory-independent and scalable state component initialization for a processor

Life of this patent

Memory-independent and scalable state component initialization for a processor

Life of this patent

Abstract

Claims17