Register freeing latency

A data processing method comprising:

• sending an instruction to an external processor to be executed by the external processor;
• allocating a specified one of a plurality of registers for a result of the instruction having been executed on the external processor;
• and
• receiving the result of the instruction having been executed on the external processor and to store the result in the specified one of the plurality of registers, wherein
• in response to a condition being met:
• the specified one of the plurality of registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.

A non-transitory computer-readable medium to store computer-readable code for fabrication of a data processing apparatus comprising:

• instruction send circuitry configured to send an instruction to an external processor to be executed by the external processor;
• allocation circuitry configured to allocate a specified one of a plurality of registers for a result of the instruction having been executed on the external processor;
• and
• data receive circuitry configured to receive the result of the instruction having been executed on the external processor and to store the result in the specified one of the plurality of registers, wherein
• in response to a condition being met:
• the specified one of the plurality of registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.