Machine code instruction
AssigneeGraphcore Limited
InventorsAlan Alexander, Simon Knowles, Godfrey Da Costa, Badreddine Noune
Life of this patent
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AssigneeGraphcore Limited
InventorsAlan Alexander, Simon Knowles, Godfrey Da Costa, Badreddine Noune
Estimating the term…
A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.
A processing device comprising:
A non-transitory computer-readable medium comprising code configured to run on a processing device, wherein the code comprises one or more instances of an instruction, taking state information comprising at least a bin count for each of a plurality of bins and a vector of floating-point values as operands, and, when executed, causes the processing device to, for a first floating-point value of the vector:
A method of operating a processor, the method comprising:
Dependencies are inferred from the claim text.