Method of manufacturing a semiconductor device including PG-aligned cells

A method of manufacturing a semiconductor device, comprising:

• forming a set of cells wherein each cell is a monostate cell lacking input terminals and output terminals including:
• forming a power-grid (PG) layer above the set of cells, including:
• forming first conductor portions which provide correspondingly a power-supply voltage and a reference voltage, and have long axes oriented substantially parallel to a first direction, wherein:
• corresponding ones of the first conductor portions of the PG layer being arranged in first pairs;
• and
• the cells being arranged to overlap at least one of the first conductor portions of the PG layer relative to the first direction;
• and
• forming a first metallization layer over the PG layer, the first metallization layer including:
• forming second conductor portions which provide correspondingly the power-supply voltage and the reference voltage and have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction, wherein:
• the cells being arranged in a repeating relationship that each cell symmetrically overlaps, relative to the first direction and the second direction, an intersection of (A) a corresponding one of the first conductor portions with (B) a corresponding one of the second conductor portions.

A method of manufacturing a semiconductor device, comprising:

• forming a set of cells wherein each cell is a monostate cell and lacking input terminals and output terminals including:
• forming a power-grid (PG) layer above the set of cells, including:
• forming a first metallization layer including:
• forming first conductor portions and second conductor portions which are configured to provide correspondingly a power-supply voltage and a reference voltage, and have long axes oriented substantially parallel to a first direction, wherein:
• corresponding ones of the first conductor portions of the first metallization layer being arranged in first pairs;
• corresponding ones of the second conductor portions of the first metallization layer being arranged in second pairs;
• and
• the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction;
• and
• forming a second metallization layer over the first metallization layer, the second metallization layer including:
• forming third conductor portions and fourth conductor portions which are configured to provide correspondingly the power-supply voltage and the reference voltage and have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction, wherein:
• the cells being arranged in a repeating relationship that each cell overlaps, relative to the first direction and the second direction, an intersection of (A) a corresponding one of the first or second pairs with (B) at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.