Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation
AssigneeSynopsys, Inc.
InventorsJiayong Le, Wenwen Chai, Li Ding
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Abstract
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
Claims10
A method for computing timing yield for an integrated circuit (IC) having a plurality of timing arcs and endpoints, a plurality of subsets of the timing arcs, each subset associated with an endpoint, the method comprising:
- a) generating a speed index associated with each timing arc of a first IC sample to determine a random delay value, wherein the same speed index is used for common timing arcs to determine the random delay values for different signal paths through the common timing arcs of an element of the integrated circuit;
- b) generating a first delay sample for each timing arc of the first IC sample based on the associated speed index, a delay distribution of the timing arc and a path context;
- c) determining a slack for each endpoint of the first IC sample;
- d) determining the worst slack from among the slacks determined for the first IC sample;
- e) repeating a) through d) for a plurality of IC samples;
- and
- f) determining timing yield for the IC based on the ratio of the number of determined worst slacks that have a non-negative value with respect to the total number of IC samples.
A computer system comprising:
- a) a storage subsystem including an Electronic Design Automation (EDA) module;
- b) a processor coupled to the storage subsystem for receiving from the storage subsystem instructions to direct the processor to:
- i. generate a speed index associated with timing arc of a first IC sample to determine a random delay value, wherein the same speed index is used for common timing arcs to determine different random delay values for different signal paths through the common timing arcs of an element of the integrated circuit;
- ii. generate a first delay sample for each timing arc of the first IC sample based on the associated speed index, a delay distribution of the timing arc and a path context;
- iii. determine a slack for each endpoint of the first IC sample;
- iv. determine the worst slack from among the slacks determined for the first IC sample;
- v. repeat i. through iv. for a plurality of IC samples;
- and
- vi. determine timing yield for the IC based on the ratio of the number of determined worst slacks that have a non-negative value with respect to the total number of IC samples.
Dependencies are inferred from the claim text.