Persistent xSPI STT-MRAM with optional erase operation

A memory device, comprising:

• a plurality of memory arrays and a non-volatile erase bit value register, wherein the memory device includes:
• a bias system connected to the plurality of memory arrays, wherein the bias system comprises one or more magnetoresistive device anti-fuse blocks;
• an error correction code datapath corresponding to each of the plurality of memory arrays;
• and
• an interface, wherein the interface is connected to the one or more magnetoresistive device anti-fuse blocks, and
• wherein the memory device is configured to:
• receive a command to program one or more of the plurality of memory arrays;
• and
• program the one or more of the plurality of memory arrays based on the command, wherein the memory device is configured to optionally erase the one or more of the plurality of memory arrays prior to the programming,
• wherein the optionally erasing the one or more of the plurality of memory arrays comprises:
• if a performance or an operation time is critical, assigning an erase bit value in the erase bit value register a first state, or
• if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state;
• and
• receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an optional erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays.

A method for programming a memory device comprising a plurality of memory arrays, the method comprising:

• receiving a write enable command at the memory device, wherein the memory device includes:
• a bias system connected to the plurality of memory arrays, wherein the bias system comprises one or more magnetoresistive device anti-fuse blocks;
• an error correction code datapath corresponding to each of the plurality of memory arrays;
• and
• an interface, wherein the interface is connected to the one or more magnetoresistive device anti-fuse blocks;
• performing one or more programming operations for one or more of the plurality of memory arrays after receiving the write enable command, wherein the method comprises optionally erasing the one or more of the plurality of memory arrays prior to the performing the one or more programming operations;
• wherein the erasing the one or more of the plurality of memory arrays comprises:
• if a performance or an operation time is critical, assigning an erase bit value in an erase bit value register a first state, or
• if the performance or operation time is not critical, assigning the erase bit value in the erase bit value register a second state;
• and
• receiving the erase bit value from the erase bit value register, wherein, when the erase bit value is in the first state, an erase command is activated such as to erase the one or more of the plurality of memory arrays, and, when the erase bit value is in the second state, an optional erase command is not activated such as not to erase the one or more of the plurality of memory arrays;
• and
• receiving a write disable command at the memory device after performing the one or more programming operations;
• and
• after programming the one or more of the plurality of memory arrays, receiving a write disable command at the memory device.