Out-of-order bit-flipping decoders for non-volatile memory devices

A system reducing a latency of a decoder in a non-volatile memory, comprising:

• a processor and a memory including instructions stored thereupon, wherein the instructions, upon execution by the processor, cause the processor to:
• receive a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices;
• perform a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices;
• and
• iteratively process the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword,
• wherein, for each column of the plurality of sorted columns of circulant matrices, the instructions upon execution by the processor cause the processor, as part of iteratively processing the plurality of sorted columns, to:
• determine a second quality metric indicative of the number of errors in the column,
• compare the second quality metric to at least one threshold, and
• in response to comparing, selectively process the column in an order determined by the sorting operation,
• wherein processing the column comprises performing a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent the parity matrix of the LDPC code to determine the candidate version of the transmitted codeword.

A non-transitory computer-readable storage medium having instructions stored thereupon for reducing a latency of a decoder in a non-volatile memory, the instructions, when executed by a processor, cause the processor to perform operations comprising:

• receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices;
• performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices;
• and
• iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword,
• wherein, for each column of the plurality of sorted columns of circulant matrices, iteratively processing the plurality of sorted columns comprises:
• determining a second quality metric indicative of the number of errors in the column,
• comparing the second quality metric to at least one threshold, and
• in response to the comparing, selectively processing the column in an order determined by the sorting operation,
• wherein processing the column comprises performing a message passing algorithm between a plurality of variable nodes and a plurality of check nodes that represent the parity matrix of the LDPC code to determine the candidate version of the transmitted codeword.