Countermeasure against fault injection attacks

An integrated circuit (IC), comprising:

• a computer resource;
• a hardware comparator circuit including a first operand register, a second operand register, first compare enable command register, a second compare enable command register, a third compare enable command register, and a scratchpad register;
• and
• a microcontroller unit (MCU) coupled to the hardware comparator circuit, the MCU configured to:
• write first value into the first operand register, a second value into the second operand register, a first compare enable command into the first compare enable command register, and a scratchpad value into the scratchpad register, the scratchpad value identifying the computer resource;
• determining that a first match exists corresponding to the first and second values;
• write a third value into the first operand register and a fourth value into the second operand register;
• write a second compare enable command into the second compare enable command register;
• and
• in response to a receipt of a success interrupt signal from the hardware comparator circuit indicating that a second match exists corresponding to the third and fourth values, writes a fifth value into the first operand register, a sixth value into the second operand register, and a second compare enable command into the second compare enable command register.

An integrated circuit (IC), comprising:

• a controller;
• a digital comparator having a first comparator input, a second comparator input, and a digital comparator output;
• a first latch having a first latch input, a first latch output, and a first enable input, the first latch input coupled to the digital comparator output, and the first enable input coupled to the controller;
• a first AND gate having a first AND gate input, a second AND gate input, and first AND gate output, the first AND gate input coupled to the first latch output, and the second AND gate input coupled to the controller;
• and
• a second latch having a second latch input, a second latch output, and a second enable input, the second latch input coupled to the digital comparator output, the second enable input coupled to the first AND gate output.