Core processor and redundant branch processor with control flow attack detection

A process for generating an executable redundant branch processor thread from a core processor thread, the core processor thread having at least data instructions and control instructions, the control instructions including a subset of branch control instructions including at least one of:

• branch control variable initialization instructions, branch control variable modification instructions, and branch instructions, the process comprising:
• identifying an execution branch control in the core processor thread;
• identifying a branch control initialization value for the execution branch control in the core processor thread;
• identifying an execution branch control in the core processor thread and inserting a branch control initialization in a corresponding location in the executable redundant branch processor thread;
• identifying a branch control conditional branch in the core processor thread and inserting a corresponding conditional branch instruction in a corresponding location of the executable redundant branch processor thread;
• identifying executable instructions in the core processor thread execution branch control which are not branch control instructions and inserting no operation (NOP) instructions in the corresponding locations of the executable redundant branch processor thread;
• where the core processor thread performs a Sum a*x(i)+y(i) operation.

A process for generating an executable redundant branch processor thread from a core processor thread, the core processor thread having at least branch control instructions and data instructions, the process comprising:

• identifying an execution loop in the core processor thread;
• identifying an initialization value for the execution loop in the core processor thread;
• identifying an execution loop variable initialization in the core processor thread and inserting an execution loop variable initialization in a corresponding location in the executable redundant branch processor thread;
• identifying an execution loop variable modification in the core processor thread and inserting an execution loop variable modification in a corresponding location in the executable redundant branch processor thread;
• creating a fault detection table containing a list of branch status values comprising at least one of:
• branch taken/not taken, branch direction, and/or a list of branch target locations, and the list of branch status values is computed by the redundant branch processor prior to execution of a program by the core processor.

A fault-detecting pipeline processor comprising:

• a core processor configured to execute control instructions and data instructions, the control instructions including a subset of branch control instructions comprising at least one of:
• a no operation (NOP) instruction, branch control variable initialization instructions, branch control variable modification instructions, conditional branch instructions, unconditional branch instructions;
• the core processor generating branch status comprising at least one of a branch taken/not taken, branch direction, and branch target;
• a redundant branch processor configured to execute only branch control instructions, the redundant branch processor generating branch status comprising at least one of a branch taken/not taken, branch direction, and branch target;
• a fault detector comparing branch status from the core processor and branch status from the redundant branch processor;
• the fault detector asserting a fault output when the corresponding branch status from the core processor and redundant branch processor are not the same value;
• where the redundant branch processor generates a list of branch status prior to execution of the core processor generating a list of branch status.