Central processing unit with asynchronous registers

A central processing unit constituted of a reduced instruction set computer architecture, comprising:

• instruction memory in which program data comprising a plurality of instructions is stored and constituted of a synchronous storage element that is synchronized with a clock signal having a predetermined frequency;
• a program counter configured to indicate an address in the instruction memory;
• an instruction decoder configured to decode an instruction fetched from the instruction memory;
• and
• a general-purpose register capable of being designated as an operand in the instruction to be decoded by the instruction decoder, wherein
• the program counter and the general-purpose register are constituted of asynchronous storage elements such that the clock signal is unnecessary when storing data in the program counter and the general-purpose register,
• the instruction fetched from the instruction memory is a single instruction directly inputted to the instruction decoder,
• the instruction decoder is the only instruction decoder connected to the instruction memory, and
• the single instruction is executed during one cycle of the clock signal, wherein the single instruction includes a decode state, an execute stage, a memory access stage, and a write back stage.