Multi-channel system architecture for managing flow of data and associated trace information

A system, comprising:

• a first hardware accelerator (HWA) comprising:
• a first buffer;
• a first scheduler communicably coupled to the first buffer;
• and
• a first direct memory access (DMA) controller;
• a system data bus;
• an event bus;
• a first memory device coupled to the first HWA via the system data bus;
• a second DMA controller coupled to the first HWA via the event bus;
• a first interface coupled to the second DMA controller via the system data bus;
• and
• a second interface coupled to the first HWA.

A method, comprising:

• transmitting, by a first direct memory access (DMA) controller, a first data set from a buffer of a processing resource to a first interface and a second data set to a first memory device over a system data bus, wherein the second data set comprises the first data set and trace data for the first data set;
• transmitting, by the first DMA controller, a first signal to a second DMA controller over an event bus, wherein the first signal indicates completion of the transmission of the first data set to the first interface;
• transmitting, by the first DMA controller, a second signal to a scheduler for the buffer over the event bus, wherein the second signal indicates completion of the transmission of the second data set to the first memory device;
• and
• in response to the second signal:
• transmitting, by the second DMA, the second data set from the first memory device to a second interface over the system data bus;
• and
• transmitting, by the second DMA, a third signal to the scheduler for the buffer over the event bus, wherein the third signal indicates completion of the transmission of the second data set to the second interface.